Since its invention over a half-century ago by Hanz Camenzind at Signetics, the familiar 555 analog timer  (in league with its updated pin-compatible CMOS descendants) has become an iconic design element incorporated into useful standardized functional blocks almost too numerous to count.  The list includes astables, bistables, monostables, voltage converters, square waves, triangle waves, saw teeth, V-to-Fs, even PWM amplifiers. 

Figure 1 illustrates one of these classics: Constant-frequency oscillator with duty cycle continuously variable from 0% to 100% via single pot P1. 

Figure 1 Diode D1 causes temperature dependence in this 555 timer circuit.

It works because the open-drain DISCHARGE pin of the 555 ramps C1 down through R1 (the top half of pot P1) during the T- half of the output cycle, and diode D1 steers C1 ramp up current from the 555 OUTPUT pin through R2  (the bottom half of pot P1) during the T+ positive output half-cycle, resulting in…

T– = R1C1 ln((2/3V+)/(1/3V+ )) = R1C1 ln(2) T+ = R2C1 ln((2/3V+  – Vd)/(1/3V+ )) Fosc = 1/(R1C1 ln(2) + R2C1 ln((2/3V+  – Vd)/(1/3V+ )))

Unfortunately, the latter two equations differ from the usual elegant 555 V+ and temperature independent timing math because of the effects of diode forward voltage drop, Vd = ~700mV – 2mV/oC for a typical silicon planar junction diode like the 1N4148.  Consequently, the timed intervals change in response to variations in both temperature and V+ power supply.  The magnitude of the changes vary inversely with nominal V+…

…and might be acceptable for some non-critical applications, but likely not when precision matters.

Figure 2 shows a fix: An inverted polarity p-channel MOSFET Q1 to steer C1 charging current without any significant voltage drop and thus implement new temperature and V+ independent  timing design equations…

T+ = R2C1 ln((2/3V+)/(1/3V+)) = R2C1 ln(2) T– = R1C1 ln((2/3V+)/(1/3V+)) = R1C1 ln(2) Fosc = 1/(ln(2)/((R1 + R2)C1)) = 1.44 / (P1C1)

Figure 2 An inverted polarity MOSFET Q1 restores timer precision.

Now the variable-duty-cycle/constant-frequency function is achieved without compromising the inherent accuracy of the 555.

The reason Q1 is connected “inverted” with its drain pin instead of source pin connected to the positive voltage source (opposite to usual practice for a p-channel FET) is to avoid forward-biasing the FET body diode when the 555 Output pin drives the drain pin low while C1 holds the R2-connected pin high.  An added benefit is, because the body diode is forward-biased when Output goes high, we’re guaranteed the FET source pin will be driven positive relative to the gate pin and the FET will go into solid saturation during the T+ interval.

An interesting aside is that a version of the Figure 1 circuit is described on page 429 of the third edition of Horowitz and Hill “The Art of Electronics.”   “The Art…” shows a Schottky diode instead of a junction type for D1 due to the former’s lower Vd.  This is a good idea as the V+ error term is significantly improved, but because the temperature coefficient of Schottkys (-2mV/oC) is similar to that of junction diodes, temperature dependent error remains mostly unchanged:

Stephen Woodward‘s relationship with EDN‘s DI column goes back quite a ways. In all, a total of 64 submissions have been accepted since his first contribution was published in 1974.

Isn’t there some MOSFET gate capacitance influence on the timing?

Undoubtedly. Ditto for parasitic capacitances of the trimpot and interconnections (e.g., PWB traces). But the magnitude of the associated effects on timing will depend on how they compare to C1.

Thanks for the comment, doc.

Is there a typo in the T+ equation for the improved circuit? Looks like T-. Where is R2?

Yes, there absolutely is (was) a typo! Please see corrected version (thanks to editor Rich). Thank you for the astute and helpful observation.

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